As DRAMs increase in memory cell density, it becomes increasingly difficult to properly align the various masks needed during the manufacturing process, thereby permitting a contact opening to be provided to the underlying active areas. Heretofore, a misalignment area was provided for in the area about the contact area to assure that electrical contact would be made to the underlying active area. As densities have further increased, improved methods have been devised to provide a so-called "self-aligning" mask. For example, the prior art methods have included a step of encapsulating a wordline in a nitride material. Subsequent etches of other materials deposited on the nitride layer were selective relative to the nitride layer such that it "self aligned" relative to the nitride covered wordline.
Although the method outlined above operated with some degree of success, it still has shortcomings which have detracted from its usefulness. For instance, some misalignment tolerance still had to be provided for. Consequently, mask misalignment could still result in providing too little room on one side of the gate for the formation of active area contacts and associated diffusion regions. As noted earlier, the goal of manufacturers continues to be to make the circuitry far more dense. Therefore, any mask misalignment can cause serious difficulties during the manufacturing process. The present method for manufacturing a field effect transistor provides a method which enables definition of controlled size active area regions adjacent to the gates.